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RTL Design Lead (Hea Job/ 32)

For Startup Specialising In Developing Electronic System For Defence
5 - 10 Years
Full Time
Up to 30 Days
Up to 18 LPA
1 Position(s)
Bangalore / Bengaluru
Posted By : HeadPro Consulting
No longer accepting applications

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Job Skills

Job Description

Job Summary

We are seeking a highly motivated and skilled RTL Design & FPGA Prototyping Engineer to join our dynamic engineering team. In this role, you will be responsible for the design, implementation, and verification of complex digital circuits using VHDL/Verilog. You will also be involved in FPGA prototyping and bring-up, working closely with cross-functional teams to deliver high-performance and reliable solutions.

Key Responsibilities

  • Design, develop, and implement complex digital circuits using VHDL/Verilog.
  • Perform RTL design, synthesis, place & route, and timing analysis.
  • Develop and execute testbenches for functional and performance verification.
  • Perform FPGA prototyping and bring-up, including debugging and troubleshooting.
  • Collaborate with cross-functional teams (e.g., software, systems) to ensure successful integration.
  • Analyze and debug complex hardware/software issues.
  • Document design specifications, test plans, and results.
  • Stay abreast of the latest advancements in FPGA technology and design methodologies.
  • Contribute to the improvement of design and verification processes.

Qualifications

  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
  • 3+ years of experience in RTL design and FPGA development.
  • Strong proficiency in VHDL/Verilog and FPGA design tools (e.g., Xilinx Vivado, Intel Quartus).
  • Experience with FPGA prototyping methodologies (e.g., PCIe, AXI).
  • Experience with scripting languages (e.g., Python, TCL).
  • Excellent analytical and problem-solving skills.
  • Strong communication and teamwork skills.
  • Ability to work independently and as part of a team.

Preferred Qualifications

  • Experience with high-speed digital design and timing closure.
  • Experience with industry-standard verification methodologies (e.g., UVM).
  • Experience with ARM/RISC-V processors.
  • Experience with DSP algorithms and implementations.
  • Experience with ASIC design flow.